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Blog Review: February 9

Build the Morello prototype; custom chips; Cryogenic PI; environmental monitoring.

Arms Mark Inskip explains how the Morello program has built a demonstration of the architecture that enables fine-grained memory protection and highly scalable software compartmentalization based on the Capability Hardware Enhanced RISC Instructions (CHERI) architectural model, from IP development and SoC design to software creation and a demonstration board.

Ansys’ John Lee examines why systems companies see custom chips as essential to maintaining their competitive advantage, especially in the areas of big data and machine learning, and why the implications will change the semiconductor industry.

Synopsis’ Plamen Asenov and Paul Wells of sureCore note that to improve quantum computing, control electronics will need to be designed to withstand near-zero temperatures and point to a cryogenic semiconductor IP development project.

Siemens Oren Manor finds that the electronics industry is coming under increasing scrutiny of its environmental performance, prompting electronics manufacturers to make critical changes such as collecting information on energy consumption and product and PCB design for sustainable manufacturing.

Cadences Vinod Khera examines how 112G SerDes technology supports the explosion of high-speed connectivity required for emerging data-intensive applications and some of its design challenges.

The ESD Alliance Bob Smith discusses challenges with 2.5D integration, 3D chip stacking and advanced packaging, and the chip design industry startup environment with Anna Fontanelli of Monozukuri.

memory analyst Jim practices examines the increasing number of voltage levels in multilevel cellular flash, from SLC to the next PLC with 5 bits per cell, and what has changed in 3D NAND and controllers to make so many voltage levels more feasible today than it has been in the past.

Intermolecular Martin McBriarty explains how atomic layer etching (ALE) can support fabrication of transistors all around the gate and how DRAM can be designed to use ALE to optimize the shape and composition of charge storage capacitors .

NXP Huanyu Gu checks how the move from L2 to L3 range is addressed and the role imaging radar plays in allowing ADAS systems to see other cars as well as pedestrians, bicycles and smaller objects.

And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Tortuga Logic’s Anders Nordstrom explains why secure software and firmware alone aren’t enough to create a tamper-proof vehicle.

Bart Stevens of Rambus offers to ensure that if attackers manage to bypass a protection mechanism, they will be faced with another layer of defense.

Siemens EDA’s Joe Hupcey III lays out the steps to formally verify that a RISC-V ISA is free from gaps and inconsistencies.

Ed Rebello from Xilinx asks to allow the hardware acceleration features of three systems to be consolidated into a single system footprint.

Infineon’s Skip Ashton dives into a new IoT standard that allows smart devices in a home to communicate with each other.

Paul Graykowski of Arteris IP discusses how to ensure that implementation and verification meet customer requirements.

Synopsys’ Dana Neustadter demonstrates how to protect digital copyrighted audio and video content as it travels over connections between devices.

Andy Jaros of Flex Logix explains why reserving an area for reconfigurability can save money later.

Cadence’s Frank Schirrmeister demonstrates the process of creating an AI accelerator that meets ISO 26262 ASIL-B specifications.

Nick Keller of Onto Innovation explains how to use the mid-IR wavelength range to measure key parameters in difficult layers.

Ron Press of Siemens EDA examines new DFT solutions that solve more complex problems.

Jamileh Davoudi of Synopsys describes how to reduce subjectivity and errors when analyzing functional safety.

Jesse Allen

Jesse Allen

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Jesse Allen is a Knowledge Center Administrator and Editor at Semiconductor Engineering.