Curvilinear masks; rigid-flexible interconnections; troubleshoot performance issues; Synchronization of the arms.
Siemens John Sturtevant finds that the patterning requirements of next-generation lithographic processes have driven lithographers to explore the benefits of curvilinear masks, and notes some of the tools that help.
Cadences Paul McLellan learns from Microsoft’s Kyle Chen and Cadence’s Suomin Cui how deep learning and electromagnetic solvers can be used to optimize high-density interconnects in multi-layer rigid-flex PCBs.
Synopsis’ Randy Fish and Guy Cortez discuss working with Advantest to find and resolve performance issues earlier in the process by enabling real-time data streaming from test stages distributed across the semiconductor supply chain to platforms analytics hosted by chipmakers.
Arms Ker Liu explains the timing approach on the Arm architecture, including atomic instructions, Arm memory ordering, and data access barrier instructions, along with an overview of typical use cases.
Ansys’ Matt Adams and Vitor Lopes Learn how hybrid digital twins merge design insights from simulation with field behavior data to enable real-time monitoring, predictive maintenance, and performance optimization.
ESD Alliance Bob Smith talks with Synopsys’ Vikram Bhatia about the pay-as-you-go approach to delivering cloud-based EDA software, changing licensing models, and what software vendors will need to provide to make it a success.
A Rambus the writer discusses with Mixel’s Justin Endo the main drivers of MIPI and I3C beyond mobile phones and upcoming trends in the IP industry.
Plus, check out the blogs featured in the latest Automotive, Security, & Pervasive Computing and Test, Measurement, & Analytics newsletters:
Arteris IP’s Stefano Lorenzini shows how to simplify the integration of configurable IP into safety-critical systems.
Synopsys’ Ron Lowman explains how benchmarks can guide the implementation of AI compression techniques without unduly affecting accuracy.
Riscure’s Marc Witteman warns that convenience features create security issues.
Andy Jaros of Flex Logix explains how to eliminate additional packaging and SerDes costs by integrating the FPGA into a SoC.
Infineon’s Danie Schneider offers a way to avoid making critical decisions based on manipulated data.
Cadence’s John Chawner is looking to increase thrust without increasing a drone’s footprint.
Cycuity’s Andreas Kuehlmann acknowledges that hardware security practices have been around for decades, but sees a new urgency to act on them.
Matthew Walsh of Siemens DISW reviews a response to the continued threat of cybersecurity attacks.
Onto Innovation’s Miki Banatwala examines how moving to the cloud can drive enterprise-wide transformations and what it takes to succeed.
Teradyne’s David Ducrocq shows the impact a technical project manager can have on the success of that project.
Synopsys’ Ash Patel reviews ATE data transfer rates for PCIe and USB.
Richard Oxland of Siemens applies product lifecycle management principles to the semiconductor value chain.
Jesse Allen
(All posts)
Jesse Allen is a Knowledge Center Administrator and Editor at Semiconductor Engineering.
